Delay lines, including lattice delay lines (LDL) provide defined delays for an input signal routed through cascaded delay elements. Lattice delay lines are implemented using delay elements configurable via control signals to allow the input signal to pass to the next delay element or direct the input signal to a return path. For a given delay, a predetermined number of cascaded delay elements provides the forward path and a return path for the input signal. Beyond a point in the cascade at which the input signal is returned, the series of delay elements are unused.
In some approaches, unused delay elements are powered off to reduce leakage current levels. Leakage current is a concern in delay element implementations using low threshold voltage devices. Reconfiguring a delay line for an increased delay includes powering on one or more delay elements that were previously powered off. A recovery time is used to allow the delay element to reach a controlled state prior to routing an input signal through the delay line.